Modern electronic systems such as radio-enabled systems and/or microprocessor systems often generate a local clock signal that is synchronized to an external clock. Such clock generation systems often include a phase lock loop (PLL) circuit, which is phase synchronized to an input reference signal. Various faults can occur in the reception of the input reference signal, such that the receiving of the input reference signal by the PLL is interrupted. Failure of the PLL circuit to properly generate a local system clock can result in a loss of the integrity of the PLL-generated system clock. A lack of prompt detection and/or mitigation of the loss of the input reference signal can result in critical system malfunctioning and/or loss of data.